Highly Integrated ISO14443A Reader IC, MF RC500

ANTENNA DRIVER OUTPUT PIN CHARACTERISTICS
The source conductance of the antenna driver pins TX1 and TX2 for driving the HIGH level can be configured via GsCfgCW in the CwConductance Register, while their source conductance for driving the LOW level is constant.
For the default configuration, the output characteristic is specified below: 

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
VOH Output Voltage HIGH TVDD = 5.0 V, IOL = 20 mA   4.97   V
TVDD = 5.0 V, IOL = 100 mA   4.85   V
VOL Output Voltage LOW TVDD = 5.0 V, IOL = 20 mA   30   mV
TVDD = 5.0 V, IOL = 100 mA   150   mV
ITX Transmitter Output Current Continuous Wave     200 mApeak

Table 20-9:Antenna Driver Output Pin Characteristics

AC Electrical Characteristics
AC SYMBOLS

Each timing symbol has five characters. The first character is always ‘t’ for time. The other characters indicate the name of a signal or the logic state of that signal (depending on position):

Designation: Signal: Designation: Logic Level:
A address H HIGH
D data L LOW
W NWR or nWait Z high impedance
R NRD or R/NW or nWrite X any level or data
L ALE or AS V any valid signal or data
C NCS    
S NDS or nDStrb and nAStrb    

Example: tAVLL = time for address valid to ALE low

AC OPERATING SPECIFICATION
Bus Timing for Separated Read/Write Strobe

SYMBOL PARAMETER MIN MAX UNIT
tLHLL  ALE pulse width 20   ns
tAVLL Multiplexed Address Bus valid to ALE low (Address Set Up Time) 15   ns
tLLAX Multiplexed Address Bus valid after ALE low (Address Hold Time) 8   ns
tLLWL ALE low to NWR, NRD low 15   ns
tCLWL NCS low to NRD, NWR low 0   ns
tWHCH NRD, NWR high to NCS high 0   ns
tRLDV NRD low to DATA valid   65 ns
tRHDZ NRD high to DATA high impedance   20 ns
tWLDV NWR low to DATA valid   35 ns
tWHDX DATA hold after NWR high (Data Hold Time) 8   ns
tWLWH NRD, NWR pulse width 65   ns
tAVWL Separated Address Bus valid to NRD, NWR low (Set Up Time) 30   ns
tWHAX Separated Address Bus valid after NWR high (Hold Time) 8   ns
tWHWL period between sequenced read / write accesses 150   ns

Table 20-10: Timing Specification for Separated Read/Write Strobe

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Note: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care.
For the multiplexed address and data bus the address lines A0 to A2 have to be connected as described in 4.3.

Bus Timing for Common Read/Write Strobe

SYMBOL PARAMETER MIN MAX UNIT
tLHLL  AS pulse width 20   ns
tAVLL Multiplexed Address Bus valid to AS low (Address Set Up Time) 15   ns
tLLAX Multiplexed Address Bus valid after AS low (Address Hold Time) 8   ns
tLLSL AS low to NDS low 15   ns
tCLSL NCS low to NDS low 0   ns
tSHCH NDS high to NCS high 0   ns
tSLDV,R NDS low to DATA valid (for read cycle)   65 ns
tSHDZ NDS low to DATA high impedance (read cycle)   20 ns
tSLDV,W NDS low to DATA valid (for write cycle)   35 ns
tSHDX DATA hold after NDS high (write cycle, Hold Time) 8   ns
tSHRX R/NW hold after NDS high 8   ns
tSLSH  NDS pulse width 65   ns
tAVSL Separated Address Bus valid to NDS low (Hold Time) 30   ns
tSHAX Separated Address Bus valid after NDS high (Set Up Time) 8   ns
tSHSL period between sequenced read/write accesses 150   ns
tRVSL R/NW valid to NDS low 8   ns

Table 20-11: Timing Specification for Common Read/Write Strobe

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Figure 20-2: Timing Diagram for Common Read/Write Strobe
Note: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines A0 to A2 have to be connected as described in 4.3.

Bus Timing for EPP

SYMBOL PARAMETER MIN MAX UNIT
tLLLH  nAStrb pulse width 20   ns
tAVLH Multiplexed Address Bus valid to nAStrb high (Set Up Time) 15   ns
tLHAX Multiplexed Address Bus valid after nAStrb high (Hold Time) 8   ns
tCLSL NCS low to nDStrb low 0   ns
tSHCH nDStrb high to NCS high 0   ns
tSLDV,R nDStrb low to DATA valid (read cycle)   65 ns
tSHDZ nDStrb low to DATA high impedance (read cycle)   20 ns
tSLDV,W nDStrb low to DATA valid (write cycle, Set up Time)   35 ns
tSHDX DATA hold after nDStrb high (write cycle, Hold Time) 8   ns
tSHRX nWrite hold after nDStrb high 8   ns
tSLSH  nDStrb pulse width 65   ns
tRVSL nWrite valid to nDStrb low 8   ns
tSLWH nDStrb low to nWait high   75 ns
tSHWL nDStrb high to nWait low   75 ns

Table 20-12: Timing Specification for Common Read/Write Strobe

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Figure 20-3: Timing Diagram for Common Read/Write Strobe
Remark: The figure does not distinguish between the Address Write Cycle and a Data Write Cycle. Take in account, that timings for the Address Write and Data Write Cycle are different. For the EPP-Mode the address lines A0 to A2 have to be connected as described in 4.3.

CLOCK FREQUENCY
The clock input is pin 1, OSCIN.

PARAMETER SYMBOL MIN TYP MAX UNIT
Clock Frequency (checked by the clock filter) fOSCIN   13.56   MHz
Duty Cycle of Clock Frequency dFEC  40 50 60 %
Jitter of Clock Edges tjitter     10 ps

The clock applied to the MF RC500 acts as time basis for the coder and decoder of the synchronous system. Therefore stability of clock frequency is an important factor for proper performance. To obtain highest performance, clock jitter shall be as small as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry .