Chip area
The size of the microcontroller die strongly affects the fragility of the chip. A larger die is more likely to break when the card is bent or twisted. Consider a telephone card carried in a wallet, for instance: the bending stresses on the card and the embedded chip are enormous. Even the finest hairline crack in the chip is sufficient to render it useless. Therefore, most card manufacturers impose an upper limit of about 25 mm2 on the chip area and demand that the layout be as nearly possible square, in order to minimize the risk of fracture.

The security policy of many card manufacturers is that the microcontrollers they use are not available on the open market. This makes it considerably more difficult to analyze the chip’s hardware, since a potential attacker normally does not have access it. However, this position has been seriously weakened by the general availability of programmable
smart cards, such as Java Card types, and it is generally no longer defensible for standard applications. Limiting the types of microcontrollers used to only a fewspecialized types (and consequently only a few manufacturers) has the disadvantage that the card manufacturer is highly dependent on the chip suppliers. If a semiconductor manufacturer experiences production problems, it is not possible to quickly switch to a different device. on the chip suppliers. If a semiconductor manufacturer experiences production problems, it is not possible to quickly switch to a different device.
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Figure 3.43 The essential functional logic units of a high-performance smart card microcontroller

Processor types
The processors used in smart cards are not special designs, but instead proven devices that have been used in other areas for a long time. In this industry, it is not usual to develop new processors for special application areas, since this is generally too expensive. In addition, it would yield a completely unfamiliar processor, for which no suitable function libraries and development tools would be available from producers of operating systems. Additionally, smart card processors must be extremely reliable. It is therefore better to rely on older type processors that have been proven in practice, rather than experimenting with the latest developments of semiconductor manufacturers. The aerospace industry, which is very interested in functional security, uses only components that are one or two generations behind the current state of the art, for the same reasons.

The transistorwas invented at the Bell labs in 1947. Intel brought out the first microprocessor in 1971, with the type designation ‘4004’. It contained 2300 transistors and had a clock frequency of 108 kHz, 45 machine instructions, 604 bytes of address space and a 4-bit data bus, yielding a processing capacity of 0.06 MIPS. Since then, the development of integrated microprocessor components has made huge strides. This is clearly shown by recent products, such as the 32-bit Pentium IV processor with 42 million transistors on 217 mm2 in 0.13-μm technology and a 2-GHz clock rate. However, the most technologically advanced processors are not used in smart cards, for the reasons that have just been stated. A total of 200,000 transistors is typical for an IC with a midrange processing capacity. Smart card microcontrollers at the lower end of the performance scale usually have an addressable memory in the range of 6 KB to 30 KB. Under these conditions, using an 8-bit memory bus does not impose any significant restrictions. The processors used generally have a CISC (complex-instruction-set computer) architecture, which means that they require several clock cycles to execute machine instructions and usually have very large instruction sets. The address range of the 8-bit processors is most often 16 bits, which allows up to 65,536 bytes to be addressed. The processor instruction sets are based on either the Motorola 6805 or Intel 8051 architecture. The semiconductor manufacturer may add supplementary instructions to the standard instruction set. Such instructions usually involve additional options for 16-bit memory addressing, which exists only in the most rudimentary form in the two instruction sets that form the basis for the instruction sets of smart card processors.

Processors in the 8-bit families are also available with extensions that allow them to address additional memory banks, in order to surmount the 64-kB limit. Access to such memory banks is controlled via special registers that map the memory banks into a specific memory region, where they can be accessed by the processor. However, this type of non-linear memory addressing has significant drawbacks. For instance, the relatively complex distribution of program code over several memory banks significantly complicates the software, thus increasing the likelihood of errors. Additional memory is also needed for bank switching functionality. Consequently, memory space expansion using memory banks is primarily a makeshift remedy that is used while awaiting the transition to processors with larger bit widths.

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Figure 3.44 Basic arrangement of a memory divided into several banks and the associated program flow. This example shows two subroutines located in two different memory banks being called from a common memory region. The numbers in parentheses indicate the sequence of events in the process

The 16-bit processors include several derivatives of existing 8051 architectures, as well as company-specific designs, such as the Renesas H8, Philips XA and Samsung CALM devices. Incidentally, for a long time theH8was the only 16-bit processor for smart card microcontrollers with a RISC-like architecture and a corresponding instruction set (‘RISC’ stands for ‘reducedinstruction-set computer’). At the upper end of the performance scale for smart card microcontrollers, both 16-bit and 32-bit types are now available. The development trend is quite clearly heading in the direction of 32-bit processors. Such processors are urgently needed in this performance class, in order to handle large memories (exceeding the 64-kB boundary) and above all to satisfy the enormous processing appetites of modern interpreter-based smart card operating systems, such as Java Card. The key selection criteria for processors include code density, power dissipation and resistance to attacks.

Among the 32-bit processors, company-specific types are presently becoming established, but two processor cores used in typical microcontroller markets have also gained an entry into the smart card realm. They are the MIPS [MIPS] and ARM [ARM] processors. The first step into the 32-bit league was taken in 1993 with the European CASCADE (‘Chip Architecture for Smart Card and portable intelligent Devices’) project. One objective of this project was to provide a high-performance processor for smart cards. The project selected the ARM 7M RISC processor, which is often used in portable equipment such as video cameras and PDAs.3 It has a 32-bit architecture and can run at up to 20 MHz with a 3-V supply voltage, while drawing only 40 mA. In 0.8-μm technology, the ARM 7 core has an area of 5.9 mm2 (3.12 × 1.9 mm), with the associated arithmetic processor for the usual public-key algorithms (RSA, DSA and EC) occupying an additional 2 mm2. The processor has both supervisor and user modes, and thus supports partitioning of the operating-system code and application code. Since originally being selected, the ARM 7 has been optimized for smart card applications, and in the form of the SC 100 (‘secure core’) it has been built into smart card microcontrollers by various semiconductor manufacturers. The next evolutionary step is a dedicated smart card variant of the ARM 9, with the type designation SC 200. A similar situation exists with the MIPS processors, which were also originally developed for other application areas.

Although 32-bit processors take up significantly more die space than 8-bit processors using the same technology, due to their wider buses and more complex internal structures, they will be used in increasing numbers in future smart card applications. The processing power that they offer is indispensable for these applications, so the disadvantages of greater power consumption and increased chip area can be accepted as the price of progress. Of course, 8-bit processors will not die out in the foreseeable future, since they provide a solid basis for inexpensive chips at the lower end of the performance scale.

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Figure 3.45 An SLE 66CX160S smart card microcontroller with an area of 21 mm2, fabricated in 0.6-μm technology with 32 kB of ROM, 16 kB of EEPROM and 1280 bytes of RAM. The two unlabeled regions on the left-hand side of the chip are the numeric coprocessor and the peripheral components (timer, random-number generator and CRC coprocessor). The five bonding pads for the electrical connections to the module contacts can be clearly seen in the photo (Photo: Infineon Technologies)

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Figure 3.46 Bond-out version of an SLE88CX720P 32-bit smart card microcontroller without final chip shielding. This microcontroller was fabricated in 0.22-μm technology and has 240 kB of ROM, 80 kB of EEPROM and 8 kB of RAM (Photo: Infineon Technologies)