EEPROM
The operating principle of an EEPROM cell is based upon the ability of a capacitor (condenser) to store electric charge over long periods. An EEPROM therefore represents a tiny capacitor that can be charged or discharged. A charged capacitor represents a logic ‘1’, a discharged capacitor represents a logic ‘0’.

In its simplest form, an EEPROM cell basically consists of a modified field effect transistor on a carrier material (substrate) made of silicon. The EEPROM cell contains an additional gate between the control gate of the field effect transistor and the substrate, which is not connected to an external power supply, and which is positioned at a very short distance (∼10 nm) from the carrier material. This so-called floating gate can be charged or discharged via the substrate using the tunnel effect, and therefore represents a capacitor. For the tunnel effect to exist there must be a sufficiently large potential difference at the thin insulating tunnelling oxidation layer between the floating gate and the substrate.

The flow of current between source and drain can be controlled by the stored charge of the floating gate. A negatively charged floating gate gives rise to a high threshold voltage between the source and drain of the field effect transistor, meaning that this is practically blocked. The current flow through the field effect transistor of an EEPROM cell is evaluated by signal amplification of the memory chip, whereby the strength of the current clearly indicates a ‘0’ or ‘1’.

To write a ‘0’ or ‘1’ to an EEPROM cell, a high positive or negative voltage is applied to the control gate, which activates the tunnel effect. The voltage required to charge the EEPROM cell is around 17 V at the control gate which falls to 12 V at the floating gate. However, RFID data carriers are supplied with 3 or 5 V from the RF interface (or a battery). Therefore a voltage of 25 V is generated from the low supply voltage of the chip using a cascaded charging pump integrated into the chip, which provides the required 17 V after stabilisation.

It takes between 5 and 10 ms to charge an EEPROM cell. The number of possible write cycles is limited to between 10 000 and 100 000 for EEPROM cells. This is because in every write operation electrons are captured by the tunnelling oxidation layer and these are never released. These electrons influence the threshold voltage of the field effect transistor, with the effect becoming greater with every write operation. As soon as this parasitic effect of the tunnelling oxidation layer becomes greater than the primary influence of the floating gate the EEPROM cell has reached its lifetime (Rankl and Effing, 1996).

A charged floating gate loses its charge due to insulation losses and quantum mechanical effects. However, according to semiconductor manufacturer’s figures, EEPROMs still provide reliable data retention for 10 years. If the EEPROM cell is nearing its lifetime, then information is only stored for short periods, which are determined by the parasitic influence of the oxide layer. For this reason, a plausibility test should be carried out on stored data using checksums (e.g. CRC) in RFID data carriers with EEPROM memories.

FRAM
High power consumption during writing and high write times of around 5–10ms have a detrimental effect on the performance of RFID systems that employ EEPROM technology. A new, non-transient memory technology, which should improve this situation, has been under development for around 20 years: ferroelectric RAM, or FRAM . At the end of the 1980s the company Ramtron was established, which collaborated with Hitachi on the development of this technology. The first RFID systems using FRAM technology were produced by the Ramtron subsidiary Racom. However, the development of FRAMs is still associated with many problems, and so RFID systems using FRAMs are still not widespread.

The principle underlying the FRAM cell is the ferroelectric effect, i.e. the capability of a material to retain an electrical polarisation, even in the absence of an electric field. The polarisation is based upon the alignment of an elementary dipole within a crystal lattice in the ferroelectric material due to the effect of an electric field that is greater than the coercive force of the material. An opposing electric field causes the opposite alignment of the internal dipole. The alignment of the internal dipole takes on one of two stable states, which are retained after the electric field has been removed.

Figure 10.34 shows a simplified model of the ferroelectric lattice. The central atom moves into one of the two stable positions, depending upon the field direction of the external electric field. Despite this, FRAM memories are completely insensitive to foreign electric interference fields and magnetic fields.

To read the FRAM cell (Figure 10.35), an electric field (UCC) is applied to the ferroelectric capacitor via a switching transistor. If the stored information represents a logic ‘1’ then the cell is in position A on the hysteresis loop. If, on the other hand, it represents a logic ‘0’, the cell is in position C. By the application of the voltage UCC we move to point B on the hysteresis loop, releasing electric charge, which is captured and evaluated by the signal amplifiers on the memory chip. The magnitude of escaping charge clearly indicates a ‘1’ or ‘0’, because a significantly greater charge escapes in the transition from state A to B than in the transition from state C to B.

After the external (read) field UCC has been removed, the FRAM cell always returns to state C, and thus a stored ‘1’ is lost, because state C represents a ‘0’. For this reason, as soon as a ‘1’ is read, the memory chip’s logic automatically performs a rewrite operation. This involves applying an opposing electric field −UCC to the ferroelectric capacitor, which changes the state of the FRAM cell, moving it to point D on the hysteresis loop. After the removal of the electric field the FRAM cell falls into state D, which recreates the originally stored state A (Haberland, 1996).Writing a ‘1’ or ‘0’ to the FRAM cell is achieved simply by the application of an external voltage −UCC or +UCC. After the voltage is removed the FRAM cell returns to the corresponding residual state A or C.

Performance Comparison FRAM – EEPROM
Unlike EEPROM cells, the write operation of a FRAM cell occurs at a high speed. Typical write times lie in the region of 0.1 µs. FRAM memories can therefore be written in ‘real time’, i.e. in the bus cycle time of a microprocessor or the cycle time of a state machine.

FRAMs also beat EEPROMs in terms of power consumption by orders of magnitude. FRAM memory was therefore predestined for use in RFID systems. However, problems in combining CMOS processors (microprocessor) and analogue circuits (RF interface) with FRAM cells on a single chip still prevent the rapid spread of this technology.