The I2C bus
Since serial, clock-synchronized data transmission protocols are uncomplicated and versatile, they are used relatively frequently. Components for use with the I2C (inter-integrated circuit) bus, which was developed by Philips, have been available since 1990. This bus is based on a bidirectional serial data lead and a serial clock lead. The definition of the I2C bus encompasses both the hardware (the two leads) and the software, in the sense of the data transmission format. Each IC on the bus can take control of the bus and send requests to other ICs connected to the bus. Since memory cards are also controlled by a synchronous clock, the I2Cbus has very quickly established itself in the smart card industry. A wide range of memory ICs has become available for use in cards. The following example is based on the SGS-Thomson ST24C04 memory chip. It has a 512-byte EEPROM that can be freely written and read. Timing computations for EEPROM programming are handled internally by the chip, so this does not have to be controlled externally. The hardware for the I2C bus consists of two lines between the terminal and the card. The serial clock (SCL) line carries the clock, which can range up to 100 kHz. This yields a data transmission rate of up to 100 kbit/s, which is relatively high for smart cards. The other line, serial data (SDA), is used bidirectionally to exchange data between the card and the terminal. The SDA line is connected to the supply voltage (Vcc) in the terminal via a pull-up resistor. Both communicating parties can only pull this line to ground. Sending a high level is therefore passive, and involves the sender switching its output to a high-impedance state (tri-state), thus allowing the pull-up resistor to pull the SDA line up to the supply voltage level. In the smart card context, the terminal is always the master of the I2C bus and the card is always the slave. Data transmission always uses single-byte packets. The most significant bit (bit 8) of the byte is sent first. Each transmission over the SDA line is initiated by a start signal and terminated by a stop signal. The start signal consists of a falling edge on the SDA line while the level on the SCL line is high. Conversely, a rising edge on the SDA line while the level on the SCL line is high indicates a stop signal. The recipient must acknowledge receipt of each byte by pulling the SDA line low for one clock cycle. The first seven bits of the first byte after the start of communications are the address of the recipient. In our example, we assume for simplicity that the address has the binary value ◦1010000x◦. Of course, this may vary depending on the chip type, and it can be chosen within certain limits for some memory ICs. The last bit in the address (x) tells the recipient whether data are to be read or written. A 1 indicates reading, while 0 is for writing. The following examples illustrate the general functions of the I2C bus as used with smart cards.

Reading from an address
There are several types of access for reading the EEPROMof a smart card. In the type described here, one byte is read at a time. However, it is also possible to read several bytes in succession. The read sequence is initiated by the start signal. The subsequent bits contain the address of the card, with the control bit set to ‘write’. This indicates to the card that it must temporarily store the following data in an internal buffer. This buffer is nothing more than a byte-oriented address pointer for the EEPROM. After the card receives the first byte, it sends an acknowledgement by grounding the SDA line for one clock cycle. After this, the terminal sends the EEPROM address to the card. Once again, the card acknowledges receipt of the data. The terminal then sends a start signal and the card address with the read bit set. On receiving this, the card sends the data from the location addressed by the pointer to the terminal. The terminal does not have to acknowledge the receipt of the data; it only sends a stop signal to the card. This completes the read sequence for one byte.

Writing to an address
As with reading data from the card’s EEPROM, there are also various modes for writing data. The simplest mode, which can be used to write a single byte anywhere in memory, is described here. Again, the sequence begins with a start signal from the terminal. This is followed by the card’s address, with the write bit set. The card acknowledges receipt and then receives from the terminal the address in the EEPROM where the data are to be written. The card acknowledges this as well, and then receives the data. After the terminal receives the third acknowledgement, which indicates that the card has received the data, it sends a stop signal. Following this, the card starts to write the received data to the EEPROM, which does not require external timing signals. This completes the writing sequence, and the byte is now stored in the EEPROM.