IS24C02,IS24C04,IS24C08,IS24C16,IS24C32,IS24C64,IS24C128,IS24C256

Serial Memory


Den Org Part No. Vcc Speed (Khz) Pkg Status Comment

1K bit 128×8 IS24C01B 2.5V-5.5V 400 wafer,module S=NOW  

2K bit 256×8 IS24C02B 2.5V-5.5V 400 wafer,module S=NOW  

4K bit 512×8 IS24C04A 2.5V-5.5V 400 wafer,module S=NOW  

8K bit 1024×8 IS24C08A 2.5V-5.5V 400 wafer,module S=NOW  

16K bit 2Kx8 IS24C16A 2.5V-5.5V 400 wafer,module S=NOW  

32K bit 4Kx8 IS24C32A 2.5V-5.5V 400 wafer,module S=NOW  

64K bit 8Kx8 IS24C64A 2.5V-5.5V 400 wafer,module S=NOW  

128K bit 16Kx8 IS24C128 2.5V-5.5V 400 wafer,module Prod  

256K bit 32Kx8 IS24C256A 2.5V-5.5V 400 wafer,module S=Q3/06

IS24C02 Card

IS24C01B / IS24C02B
1K-bit/2K-bit 2-WIRE SERIAL CMOS EEPROM
FEATURES
• Two-Wire Serial Interface, I2CTM compatible
– Bi-directional data transfer protocol
• Wide Voltage Operation
– Vcc = 1.8V to 5.5V
• 400 KHz (2.5V) and 1 MHz (5.0V) compatibility
• Low Power
– Standby Current: 1 μA or less (1.8V)
– Read Current: 2 mA or less (5.0V)
– Write Current: 3 mA or less (5.0V)
• Hardware Data Protection
– Write Protect Pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
5 ms max. @ 2.5V
• Memory Organization:
– IS24C01B: 128×8 (1K bits)
– IS24C02B: 256×8 (2K bits)
• 8-Byte Page Write Buffer
• High Reliability
– Endurance: 1,000,000 Cycles
– Data Retention: 100 Years
• Industrial temperature grade
• Packages: SOIC/SOP, TSSOP, DFN, and UDFN.

The IS24C01B and IS24C02B are EEPROM devices that use the industrial standard 2-wire, I2C, interface for communications. The IS24C01B and IS24C02B contain a memory array of 1K-bits (128 x 8 ) and 2K-bits (256 x 8 ), respectively. Each device is organized into 8 byte pages for page write mode.

This EEPROM operates in a wide voltage range of 1.8V to 5.5V to be compatible with most application voltages. ISSI designed this device family to be a practical, low-power 2-wire EEPROM solution. The devices are offered in lead-free, RoHS, halogen free or Green. The available package types are 8-pin SOIC, TSSOP, DFN, and UDFN.

The IS24C01B/02B maintains compatibility with the popular 2-wire bus protocol, so it is easy to use in applications implementing this bus type. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as this device. The bit stream over the SDA line includes a series of bytes, which identifies a
particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS24C01B/02B has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus.

DEVICE OPERATION
IS24C01B/02B features serial communication and supports a bi-directional 2-wire bus transmission protocol called I2CTM.

2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and a Serial Clock line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as receivers. The bus is controlled by Master device that generates the SCL, controls the bus access, and generates the Stop and Start conditions. The IS24C01B/02B is the Slave device on the bus.

The Bus Protocol:
– Data transfer may be initiated only when the bus is not busy
– During a data transfer, the SDA line must remain stable whenever the SCL line is high. Any changes in the SDA line while the SCL line is high will be interpreted as a Start or Stop condition.

The state of the SDA line represents valid data after a Start condition. The SDA line must be stable for the duration of the High period of the clock signal. The data on the SDA line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition.

Start Condition
The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA when SCL is High. The EEPROM monitors the SDA and SCL lines and will not respond until the Start condition is met.

Stop Condition
The Stop condition is defined as a Low to High transition of SDA when SCL is High. All operations must end with a Stop condition.

Acknowledge (ACK)
After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging device pulls down the SDA line.

Reset
The IS24C01B/02B contains a reset function in case the 2-wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. The reset is caused when the Master device creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level on SDA.)

Standby Mode
Power consumption is reduced in standby mode. The IS24C01B/02B will enter standby mode: a) At Power-up, and remain in it until SCL or SDA toggles; b) Following the Stop signal if a no write operation is initiated; or c) Following any internal write operation.

DEVICE ADDRESSING
The Master begins a transmission by sending a Start condition. The Master then sends the address of the particular Slave devices it is requesting. The Slave device (Fig. 5) address is 8 bits.

The four most significant bits of the Slave device address are fixed as 1010 for the IS24C01B/02B. The next three bits of the Slave address are specific for each of the EEPROM. The bit values enable access to multiple memory blocks or multiple devices. The IS24C01B/02B uses the three bits A0, A1, and A2 in a comparison with the hard-wired input values on the A0, A1, and A2 pins. Up to eight units may share the 2-wire bus.

The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.

After the Master transmits the Start condition and Slave address byte (Fig. 5), the appropriate 2-wire Slave (eg. IS24C02B) will respond with ACK on the SDA line. The Slave will pull down the SDA on the ninth clock cycle, signaling that it received the eight bits of data. The selected EEPROM then prepares for a Read or Write operation by monitoring the bus.

WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the byte address that is to be written into the address pointer of the IS24C01B/02B. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24C01B/02B acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device.

Page Write
The IS24C01B/02B is capable of 8-byte Page-Write operation. A Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 7 more bytes. After the receipt of each data word, the EEPROM responds immediately with an ACK on SDA line, and the three lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 8 bytes prior to issuing the Stop condition, the address counter will “roll over,” and the previously written data will be overwritten. Once all 8 bytes are received and the Stop condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24C01B/02B in a single Write cycle. All inputs are disabled until completion of the internal Write cycle.

Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop condition is issued to indicate the end of the host’s Write operation, the IS24C01B/02B initiates the internal Write cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed by the Slave address for a Write operation. If the EEPROM is still busy with the Write operation, no ACK will be returned. If the IS24C01B/02B has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation.

Read OPERATION
Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave address is set to “1”. There are three Read operation options: current address read, random address read and sequential read.

Current Address Read
The IS24C01B/02B contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the EEPROM receives the Slave Addressing Byte with a Read operation (R/W bit set to “1”), it will respond an ACK and transmit the 8-bit data byte stored at address location n+1. The Master should not acknowledge the transfer but should generate a Stop condition so the IS24C01B/02B discontinues transmission. If ‘n’ is the last byte of the memory, the data from location ’0′ will be transmitted.

Random Address Read
Selective Read operations allow the Master device to select at random any memory location for a Read operation. The Master device first performs a ‘dummy’ Write operation by sending the Start condition, Slave address and byte address of the location it wishes to read. After the IS24C01B/02B acknowledges the byte address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to one. The EEPROM then responds with its ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition.

Sequential Read
Sequential Reads can be initiated as either a Current Address Read or Random Address Read. After the IS24C01B/02B sends the initial byte sequence, the Master device now responds with an ACK, indicating it requires additional data from the IS24C01B/02B. The EEPROM continues to output data for each ACK received. The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data word to be read, followed by a Stop condition. The data output is sequential, with the data from address n followed by the data from address n+1,n+2 … etc. The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential Read operation. When the memory address boundary of 127 or 255 (depending on the device) is reached, the address counter “rolls over” to address 0, and the device continues to output data.

IS24C02 Card/ IS24C04 Card / IS24C08 Card / IS24C16 Card.

IS24C02A / IS24C04A / IS24C08A / IS24C16A
2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM
FEATURES
• Two-Wire Serial Interface, I2CTM Compatible
– Bi-directional data transfer protocol
• Wide Voltage Operation
– Vcc = 1.8V to 5.5V
• 400 KHz (2.5V) and 1 MHz (5.0V) Compatible
• Low Power
– Standby Current less than 1 μA (1.8V)
– Read Current less than 2 mA (5.0V)
– Write Current less than 3 mA (5.0V)
• Hardware Data Protection
– Write Protect Pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
5 ms max @ 2.5V
• Memory Organization
–IS24C02A: 256×8 (one block of 256 bytes)
–IS24C04A: 512×8 (two blocks of 256 bytes)
–IS24C08A: 1024×8 (four blocks of 256 bytes)
–IS24C16A: 2048×8 (eight blocks of 256 bytes)
• 16 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 100 Years
• Industrial temperature grade
• Packages: SOIC/SOP, TSSOP, PDIP, MSOP, DFN, CSP

The IS24C02A, IS24C04A, IS24C08A, and IS24C16A are EEPROM devices that use the industrial standard 2-wire interface for communications. The IS24C02A, IS24C04A, IS24C08A, and IS24C16A contain a memory array of 2K-bits (256 x 8), 4K-bits (512 x 8), 8K-bits (1,024 x 8), and 16K-bits (2,048 x 8), respectively. Each device is organized into 16 byte pages for page write mode.

This EEPROM operates in a wide voltage range of 1.8V to 5.5V to be compatible with most application voltages. ISSI designed this device family to be a practical, low-power 2-wire EEPROM solution. The devices are offered in Lead-free, RoHS, halogen free or Green. The available package types are 8-pin SOIC/SOP, TSSOP, PDIP, MSOP, DFN and CSP.

The IS24C02A/04A/08A/16A maintains compatibility with the popular 2-wire bus protocol, so it is easy to use in applications implementing this bus type. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as this device. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS24C02A/04A/08A/16A has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus.

IS24C32 Card / IS24C64 Card
IS24C32A / IS24C64A/B
65,536 bit/32,768 bit 2-WIRE SERIAL CMOS EEPROM
FEATURES
• Two-Wire Serial Interface
–Bi-directional data transfer protocol
• 400 KHz (I2C Protocol) Compatibility
• Low Power CMOS Technology
–Standby Current less than 6 μA (5.0V)
–Read Current less than 2 mA (5.0V)
–Write Current less than 3 mA (5.0V)
• Flexible Voltage Operation
–Vcc = 1.8V to 5.5V for –2 version
–Vcc = 2.5V to 5.5V for –3 version
• Hardware Data Protection
–IS24C32A/64A: WP protects entire array
–IS24C64B: WP protects top quarter of array
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• 8-pin PDIP, 8-pin SOIC and 8-pin TSSOP packages
• Self time write cycle with auto clear
5 ms @ 2.5V
• Organization:
–IS24C32A: 4Kx8 (128 pages of 32 bytes)
–IS24C64A/B: 8Kx8 (256 pages of 32 bytes)
• 32 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 100 Years
• Commercial and Industrial temperature ranges

The IS24C32A and IS24C64A/B are electrically erasable PROM devices that use the standard 2-wire interface for communications. The IS24C32A and IS24C64A/B contain a memory array of 32Kbits (4K x 8 ) and 64K-bits (8K x 8 ), respectively. Each device is organized into 32 byte pages for page write mode.

This EEPROM is offered in wide operating voltages of 1.8V to 5.5V (IS24Cxx-2) and 2.5V to 5.5V (IS24Cxx-3) to be compatible with most application voltages. ISSI designed this device family to be a practical, low-power 2-wire EEPROM solution. The devices are available in 8-pin PDIP, 8-pin SOIC and 8-pin TSSOP packages.

The IS24C32A/64A/64B maintains compatibility with the popular 2-wire bus protocol, so it is easy to use in applications implementing this bus type. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as this device. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS24C32A/64A/64B has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus.

IS24C128 Card / IS24C256 Card
IS24C128-2/3 / IS24C256-2/3:
262,144-bit/131,072-bit 2-WIRE SERIAL CMOS EEPROM
FEATURES
• Low Power CMOS Technology
– Standby Current less than 10 μA (5.5V)
– Read Current (typical) less than 1 mA (5.5V)
– Write Current (typical) less than 3 mA (5.5V)
• Low Voltage Operation
– IS24C256-2 & IS24C128-2: Vcc = 1.8V to 5.5V
– IS24C256-3 & IS24C128-3: Vcc = 2.5V to 5.5V
• 100 KHz (1.8V), 400 KHz (2.5V) and 1MHz (5V) Compatibility
• Hardware Data Protection
– Write Protect Pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
– 5 ms @ 2.5V
• Organization:
– IS24C256-2 and IS24C256-3: 32,768×8
– IS24C128-2 and IS24C128-3: 16,384×8
• 64-Byte Page Write Buffer
• Two-Wire Serial Interface
– Bi-directional data transfer protocol
• High Reliability
– Endurance: 1,000,000 Cycles
– Data Retention: 100 Years
• Commercial and Industrial temperature ranges
• 8-pin PDIP, 8-Pin SOIC, and 14-pin TSSOP

The IS24C128-2 is a 1.8V (1.8V-5.5V) 128K-bit (16384 x 8 ) Electrically Erasable PROM, IS24C128-3 is a 2.5V (2.5V-5.5V) 128K-bit (16384 x 8 ) Electrically Erasable PROM, IS24C256-2 is a 1.8V (1.8V-5.5V) 256K-bit (32768 x 8 ) Electrically Erasable PROM and the IS24C256-3 is a 2.5V (2.5V-5.5V) 256K-bit (32768 x 8 ) Electrically Erasable PROM.

The IS24CXXX (IS24C128-2, IS24C128-3, IS24C256-2 and IS24C1256-3) family is a low-cost and low voltage 2-wire Serial EEPROM. It is fabricated using ISSI’s advanced CMOS EEPROM technology and provides a low power and low voltage operation. The IS24CXXX family features a write protection feature, and is available in 8-pin DIP, 8-pin SOIC, and 14-pin TSSOP packages.