ISO/IEC 14443 higher bit rates with Micore

Mifare, Micore, ISO/IEC14443, Higher bit rates, Register settings
How to enable and use higher bit rates according to the ISO/IEC14443 using the MF RC530, MF RC531, or the CL RC632.

The ISO/IEC14443 offers communication data rates from 106 kbit/s (standard) up to 848 kbit/s. These higher bit rates (212, 424, and 848 kbit/s) are supported by the Micore ICs MF RC531 and CL RC632 (and MF RC530 for ISO/IEC 14443A only). Depending on the contactless smart cards, the bit rates can be different in the uplink (PICC to PCD) and downlink (PCD to PICC). The bit rates have to be selected according to the ISO/IEC14443. This application note describes how to use the higher bit rates, how to use the Micore ICs with the higher bit rates, and it gives some hints, what has to be considered during the PCD design. So it covers hardware related topics as well as software related ones. This application note does replace neither any of the ISO/IEC documents nor any of the relevant datasheets.

Table 1: Abbreviations

Table description (optional)

Acronym Description
PCD proximity coupling device (“reader”)
Micore Mifare and I-Code reader IC family (here only the MFRC530,
  MF RC531, and the CL RC632)
PPS Protocol Parameter Selection
RATS Request for Answer To Select
ATS Answer To Select
DS Divisor Send (PICC to PCD)
DR Divisor Receive (PCD to PICC)
ATQB Answer To reQuest type B
RF Radio Frequency
fc Carrier frequency (13.56MHz)
Mfout Signal available at pin 4 of the Micore IC, used for triggering the oscilloscope.

Hexadecimal numbers are noted with a leading “0x”.

ISO/IEC 14443A
Selecting higher bit rates

During the RATS and ATS (see [9]) the PCD and the PICC exchange the necessary parameters for the protocol. In the interface byte TA(1) of the ATS the PICC returns the information whether it supports higher bit rates or not, and if so, which bit rates can be used in which direction.

Table 2: Interface byte TA
  Bit number Meaning, if set to “1”
  B8 Only the same bit rate in both directions
DS B7 848 kbit/s supported (PICC to PCD)2
B6 424 kbit/s supported (PICC to PCD)
B5 212 kbit/s supported (PICC to PCD)
  B4 RFU, must be “0”
DS B3 848 kbit/s supported (PCD to PICC)
B2 424 kbit/s supported (PCD to PICC)
B1 212 kbit/s supported (PCD to PICC)

The PCD shall use the PPS Request to switch to a higher bit rate, using the parameter 1 to request the bit rate. In case no higher bit rates are used, the PPS has to be skipped by the PCD.

Table 3: Parameter 1 of the PPS Request
B8 B7 B6 B5 B4 B3 B2 B1
0 0 0 0 DSI   DRI  


Table 4: Coding of DSI and DRI
DSI, DRI 11bin 10bin 01bin 00bin
D 8 4 2 1
Bit rate 848 kbit/s 424 kbit/s 212 kbit/s 106 kbit/s

According to the ISO/IEC 14443 the PICC just acknowledges the PPS Request. The following command then is the first command using the selected higher bit rates.
Remark: Sending and Receiving in the means of ISO/IEC 14443 is related to the PICC, in this document Sending and Receiving is related to the PCD!

Setting higher bit rates with Micore
Enabling higher bit rates can be done automatically, using the function Mf500PcdSetAttrib in [1]. All the relevant register settings are listed there and in the following tables Table 5: and Table 6:.
Remark: Switching back to the default bit rate can be done with the function Mf500PcdSetDefaultAttrib

Table 5: ISO/IEC14443A HBR Register Settings PICC to PCD

Micore register sending for receiving ISO/IEC14443A HBR

Register Name Address 1064 212 424 848
RegCoderControl 0×14 0×19 0×11 0×09 0×01
RegModWidth 0×15 0×13 0×07 0×03 0×01


RegRxControl1 0×19 0×73 0×53 0×33 0×13
Table 6: ISO/IEC14443A HBR Register Settings PICC to PCD

Micore register settings for receiving ISO/IEC14443A HBR

Register Name Address 1064 212 424 848
RegRxControl1 0×19 0×73 0×53 0×33 0×13
RegDecoderControl 0x1A 0×08 0×09 0×09 0×09
RegRxThreshold 0x1C 0×88 0×50 0×50 0×50
RegBPSKDemControl  0x1D x5 0x0C 0x0C 0x0C

Remark: The required speed of the microcontroller should be considered (especially when using frame sizes >64 bytes) as well as the application related limitations regarding the overall transaction time.