The MF RC500 is member of a new family of highly integrated reader ICs for contactless communication at 13.56 MHz. This new reader IC family utilises an outstanding modulation and demodulation concept completely integrated for all kinds of passive contactless communication methods and protocols at 13.56 MHz. The MF RC500 is pin- compatible to the MF RC530, the MF RC531 and the SL RC 400. The MF RC500 supports all layers of ISO14443A. The internal transmitter part is able to drive an antenna designed for proximity operating distance (up to 100 mm) directly without additional active circuitry. The receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from ISO14443A compatible transponders. The digital part handles ISO14443A framing and error detection (Parity & CRC). Additionally it supports the fast CRYPTO 1 security algorithm to authenticate MIFARE® Classic (e.g. MIFARE® Standard 1k and MIFARE® Standard 4k) products. A comfortable parallel interface which can be directly connected to any 8-bit μ-Processor gives high flexibility for the reader/terminal design.

Features
-Highly integrated analogue circuitry to demodulate and decode card response
-Buffered output drivers to connect an antenna with minimum number of external components
-Proximity operating distance (up to 100 mm)
-Supports ISO 14443A part 1- 4
-Supports MIFARE® Classic protocol
-Crypto1 and secure non-volatile internal key memory
-Pin-compatible to the MF RC530, MF RC531, SL RC400 and MF RC632
-Parallel μ-Processor interface with internal address latch and IRQ line
-Flexible interrupt handling
-Automatic detection of parallel μ-Processor interface type
-Comfortable 64 byte send and receive FIFO-buffer
-Hard reset with low power function
-Power down mode per software
-Programmable timer
-Unique serial number
-User programmable start-up configuration
-Bit- and byte-oriented framing
-Independent power supply pins for digital, analogue and transmitter part
-Internal oscillator buffer to connect 13.56 MHz quartz, optimised for low phase jitter
-Clock frequency filtering
-3.3 V operation for transmitter (antenna driver) in short range applications

MF RC500 Ordering Information: MF RC500 01T/0FE, SO32, Small Outline Package; 32 leads.

Pin Description
Pin Types: I…Input; O…Output; PWR…Power

Pin Description    
Pin Types: I…Input; O…Output; PWR…Power
PIN SYMBOL TYPE DESCRIPTION
1 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator.
This pin is also the input for an externally generated clock (fosc = 13.56 MHz).
2 IRQ O Interrupt Request: output to signal an interrupt event
3 MFIN I MIFARE Interface Input: accepts a digital, serial data stream according to
ISO14443A (MIFARE)
4 MFOUT O MIFARE Interface Output: delivers a serial data stream according to ISO14443A (MIFARE)
5 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier
6 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2
7 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier
8 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
9 NCS I Not Chip Select: selects and activates the μ-Processor interface of the MF RC500
10 NWR I Not Write: strobe to write data (applied on D0 to D7) into the MF RC500 register
R/NW I Read Not Write: selects if a read or write cycle shall be performed.
nWrite I Not Write: selects if a read or write cycle shall be performed
11 NRD I Not Read: strobe to read data from the MF RC500 register (applied on D0 to D7)
NDS I Not Data Strobe: strobe for the read and the write cycle
nDStrb I Not Data Strobe: strobe for the read and the write cycle
12 DVSS PWR Digital Ground
13-20 D0 to D7 I/O 8 Bit Bi-directional Data Bus
AD0 to AD7 I/O 8 Bit Bi-directional Address and Data Bus
21 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
AS I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
nAStrb I Not Address Strobe: strobe signal to latch AD0 to AD5 into the internal address latch
when LOW.
22 A0 I Address Line 1: Bit 0 of register address
nWait O Not Wait: signals with LOW that an access-cycle may started and with HIGH that it
may be finished.
23 A1 I Address Line 1: Bit 1 of register address
24 A2 I Address Line 2: Bit 2 of register address
25 DVDD PWR Digital Power Supply
26 AVDD PWR Digital Power Supply
27 AUX O Auxiliary Output: This pin delivers analog test signals. The signal delivered on this
output may be selected by means of the TestAnaOutSel Register.
28 AVSS PWR Analog Ground
29 RX I Receiver Input: Input pin for the cards response, which is the load modulated 13.56
MHz energy carrier, that is coupled out from the antenna circuit.
30 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage.
Note: It has to be supported by means of a 100 nF block capacitor.
31 RSTPD I Reset and Power Down: When HIGH, internal current sinks are switched off, the
oscillator is inhibited, and the input pads are disconnected from the outside world.
With a negative edge on this pin the internal reset phase starts.
32 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
Table 3-1: MF RC500 Pin Description