Highly Integrated ISO14443A Reader IC, MF RC500

The phases executed during the start up are shown in the following figure.

Hard Power Down Phase
The Hard Power Down Phase is active during the following cases:
1. Power On Reset caused by power up at pin DVDD (active while DVDD is below the digital reset threshold)
2. Power On Reset caused by power up at pin AVDD (active while AVDD is below the analog reset threshold)
3. A HIGH level on pin RSTPD (active while pin RSTPD is HIGH)
In case three, HIGH level on pin RSTPD, has to be at least 100μs long (tPD >= 100μs). Shorter phases will not necessarily result in the reset phase tReset.
The slew rate of rising/falling edge on pin RSTPD is not critical because pin RSTPD is a schmitt-trigger input.

Reset Phase
The Reset Phase follows the Hard Power Down Phase automatically. One’s the oscillator is running stable, it takes 512 clocks. During the Reset Phase, some of the register bits are pre-set by hardware. The respective reset values are given in the description of each register (see 5.2.).
Note: If the internal oscillator is used, you have to take into account that it is supplied by AVDD and that it will take a certain time tosc until the oscillator is stable.

Initialising Phase
The Initialising Phase follows the Reset Phase automatically. It takes 128 clocks. During the Initialising Phase the content of the E²PROM blocks 1 and 2 is copied into the registers 10hex to 2Fhex. (see 6.3)
Note: At production test, the MF RC500 is initialised with default configuration values. This reduces the μ-Processors effort for configuring the device to a minimum.

A certain initialising sequence shall be applied to enable proper μ-Processor interface type detection and to synchronise the μ-Processor’s and the MF RC500’s Start Up. During the Start Up Phase the Command value reads as 3Fhex, after the oscillator delivers a stable clock frequency with an amplitude of >90% of the nominal 13.56MHz clock. At the end of the Initialising Phase the MF RC500 enters the Idle Command automatically. Consequently the Command value changes to 00hex. To ensure proper detection of the μ-Processor interface, the following sequence shall be executed:
–Read from the Command-Register until the 6-bit register value for Command is 00hex. The internal initialisation phase is now completed and the MF RC500 is ready to be controlled.
–Write the value 80hex to the Page-Register to initialise the μ-Processor interface.
–Read the Command-Register. If its value is 00hex the μ-Processor interface initialisation was successful.
Having done the interface initialisation, the linear addressing mode can be activated by writing 0×00 to the page register(s).


The clock applied to the MF RC500 acts as time basis for the coder and decoder of the synchronous system. Therefore stability of the clock frequency is an important factor for proper performance. To obtain highest Performance, clock jitter has to be as small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry. If an external clock source is used, the clock signal has to be applied to pin OSCIN. In this case special care for clock duty cycle and clock jitter is needed and the clock quality has to be verified. It needs to be in accordance with the specifications in chapter 20.5.3.
Remark: We recommend not to use an external clock source.

The signal delivered on TX1 and TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly, using a few passive components for matching and filtering (see chapter 18). For that, the output circuitry is designed with a very low impedance source resistance. The signal of TX1 and TX2 can be controlled via the TxControl Register.

Configuration of TX1 and TX2
The configuration possibilities of TX1 are described in the table below:

Register Configuration in TxControl Envelope Signal on TX1
1 0 LOW
1 1 13.56 MHz energy carrier

Table 13-1: Configurations of Pin TX1

The configuration possibilities of TX2 are described in the table below:

Register Configuration in TxControl Envelope Signal on TX2
    0 0 LOW
  0   1 13.56 MHz energy carrier
  0 HIGH
1   1 1 13.56 MHz energy carrier, 180° phase shift relative to TX1
1 0 X 13.56 MHz energy carrier
1 X 13.56 MHz energy carrier, 180° phase shift relative to TX1

Table 13-2: Configurations of Pin TX2

Operating Distance versus Power Consumption
The user has the possibility to find a trade-off between maximum achievable operating distance and power consumption using different antenna matching circuits by varying the supply voltage at the antenna driver supply pin TVDD. Different antenna matching circuits are described in the Application Note, MIFARE Design of MF RC500 Matching Circuit and Antennas.

Pulse Width
The envelope carries the information of the data signal that shall be transmitted to the card done by coding the data signal according to the Miller code. Furthermore, each pause of the Miller coded signal again is coded as a pulse of certain length. The width of this pulse can be adjusted by means of the ModWidth Register.

The MF RC500 employs an integrated quadrature-demodulation circuit which extracts the ISO14443-A subcarrier signal from the 13.56 MHz ASK-modulated signal applied to pin RX. The quadrature-demodulator uses two different clocks, Q- and I-clock, with a phase shift of 90° between them. Both resulting subcarrier signals are amplified, filtered and forwarded to a correlation circuitry. The correlation results are evaluated, digitised and passed to the digital circuitry.
For all processing units various adjustments can be made to obtain optimum performance.

Block Diagram
Figure 14-1 shows the block diagram of the receiver circuitry. The receiving process includes several steps. First the quadrature demodulation of the carrier signal of 13.56 MHz is done. To achieve an optimum in performance an automatic clock Q calibration is recommended (see 14.3.1). The demodulated signal is amplified by an adjustable amplifier. A correlation circuit calculates the degree of similarity between the expected and the received signal. The bit phase register allows aligning the position of the correlation intervals with the bit grid of the received signal. In the evaluation and digitizer circuitry the valid bits are detected and the digital results are send to the FIFO register. Several tuning steps in this circuit are possible.
The user may observe the signal on its way through the receiver as shown in the block diagram above. One signal at a time may be routed to pin AUX using the TestAnaSelect-Register as described in 19.3.

Putting the Receiver into Operation
In general, the default settings programmed in the Start Up Initialisation File are suitable to use the MF RC500 for data communication with MIFARE cards. However, in some environments specific user settings may achieve better performance.

The quadrature demodulation concept of the receiver generates a phase signal I-clock and a 90° shifted quadrature signal Q-clock. To achieve an optimum demodulator performance, the Q- and the I-clock have to have a difference in phase of 90°. After the reset phase of the MF RC500, a calibration procedure is done automatically. It is possible to have an automatic calibration done at the ending of each Transceive command. To do so, the ClkQCalib bit has to be configured to a value of 0. Configuring this bit to a constant value of 1 disables all automatic calibrations except the one after the reset sequence. It is also possible to initiate one automatic calibration by software. This is done with a 0 to 1 transition of bit ClkQCalib.
The details:

Note: The duration of the automatic clock Q calibration takes 65 oscillator periods (approx. 4,8μs).
The value of ClkQDelay is proportional to the phase shift between the Q- and the I-clock. The status flag ClkQ180Deg shows, that the phase shift between the Q- and the I-clock is greater than 180°.
–The startup configuration file enables an automatically Q-clock calibration after the reset.
–While ClkQCalib is 1, no automatic calibration is done. Therefore leaving this bit 1 can be used to
permanently disable the automatic calibration.
–It is possible to write data to ClkQDelay via the μ-Processor. The aim could be a disabling of the automatic calibration and to pre-set the delay by software. But notice, that configuring the delay value by software requires that bit ClkQCalib has already been set to 1 before and that a time interval of at least 4.8μs has elapsed since then. Each delay value must be written with the ClkQCalib bit set to 1. If ClkQCalib is 0 the configured delay value will be overwritten by the next interval automatic calibration.

The demodulated signal has to be amplified with the variable amplifier to achieve the best performance. The gain of the amplifiers can be adjusted by means of the register bits Gain[1:0]. The following gain factors are selectable:

Register Setting Gain Factor [dB] (Simulation Results)
0 20
1 24
2 31
3 35

Table 14-1: Gain Factors for the Internal Amplifier

The correlation circuitry calculates the degree of matching between the received and an expected signal. The output is a measure for the amplitude of the expected signal in the received signal. This is done for both, the Q- and the I-channel. The correlator delivers two outputs for each of the two input channels, resulting in four output signals in total. For optimum performance, the correlation circuitry needs the phase information for the signal coming from the card. This information has to be defined by the μ-Processor by means of the register BitPhase[7:0]. This value defines the phase relation between the transmitter and receiver clock in multiples of tBitPhase =
1/13.56 MHz.

For each bit-half of the Manchester coded signal the correlation results are evaluated. The evaluation and digitizer circuit decides from the signal strengths of both bit-halves, whether the current bit is valid, and, if it is valid, the value of the bit itself or whether the current bit-interval contains a collision.
To do this in an optimum way, the user may select the following levels:
–MinLevel: Defines the minimum signal strength of the stronger bit-half’s signal for being considered valid.
–CollLevel: Defines the minimum signal strength that has to be exceeded by the weaker half-bit of the Manchester-coded signal to generate a bit-collision. If the signal’s strength is below this value, a 1 and 0 can be determined unequivocally. CollLevel defines the minimum signal strength relative to the amplitude of the stronger half-bit.
After transmission of data, the card is not allowed to send its response before a certain time period, called frame guard time in the standard ISO14443. The length of this time period after transmission shall be set in the RxWait-Register. The RxWait-Register defines when the receiver is switched on after data transmission to the card in multiples of one bit-duration. If register bit RcvClkSelI is set to 1, the I-clock is used to clock the correlator and evaluation circuits. If set to 0, the Q-clock is used.
Note: It is recommended to use the Q-clock.

Two main blocks are implemented in the MF RC500. A digital circuitry, comprising state machines, coder and decoder logic and so on and an analog circuitry with the modulator and antenna drivers, receiver and amplification circuitry. The interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins MFIN and MFOUT.
This topology supports, that the analog part of the one MF RC500 may be connected to the digital part of another device.

Block Diagram
Figure 15-1 describes the serial signal switches. Three different switches are implemented in the serial signal switch in order to use the MF RC500 in different configurations. The serial signal switch may also be used during the design In phase or for test purposes to check the transmitted and received data. Chapter 19.2, describes analog test signals as well as measurements at the serial signal switch.

The following chapters describe the relevant registers used to configure and control the serial signal switch.

Registers Relevant for the Serial Signal Switch
The flags DecoderSource define the input signal for the internal Manchester decoder in the following way:

DecoderSource Input Signal for Decoder
0 Constant 0
1 Output of the analog part. This is the default configuration.
2 Direct connection to MFIN, expecting a 847.5 kHz sub-carrier signal modulated by a Manchester coded signal.
3 Direct connection to MFIN, expecting a Manchester coded signal.

Table 15-1: Values for DecoderSource

ModulatorSource defines the signal that modulates the transmitted 13.56 MHz energy carrier. The modulated signal drives the pins TX1 and TX2.

ModulatorSource Input Signal for Modulator
0 Constant 0 (energy carrier off at pin TX1 and TX2).
1 Constant 1 (continuous energy carrier delivered at pin TX1 and TX2).
2 Modulation signal (envelope) from the internal coder. This is the default configuration.
3 Direct connection to MFIN, expecting a Miller pulse coded signal.

Table 15-2: Values for ModulatorSource

MFOUTSelect selects the output signal which is routed to the pin MFOUT.

MFOUTSelect Signal Routed to Pin MFOUT
0 Constant Low
1 Constant High
2 Modulation signal (envelope) from the internal coder.
3 Serial data stream that is to be transmitted (same as for MFOUTSelect = 2, but not coded by the Miller pulse coder yet).
4 Output signal of the receiver circuit (card modulation signal regenerated and delayed)
5 Output signal of the subcarrier demodulator (Manchester-coded card signal)

Table 15-3: Values for MFOUTSelect
Note: To use MFOUTSelect, the value of test signal control bit SignalToMFOUT has to be 0.