The MF RC500 indicates certain events by setting bit IRq in the PrimaryStatus-Register and, in addition, by activating pin IRQ. The signal on pin IRQ may be used to interrupt the μ-Processor using its interrupt handling capabilities. This allows the implementation of efficient μ-Processor software.

The following table shows the integrated interrupt flags, the related source and the condition for its setting. The interrupt flag TimerIRq indicates an interrupt set by the timer unit. The setting is done when the timer decrements from 1 either down to zero (TAutoRestart flag disabled) or to the TPreLoad value if TAutoRestart is enabled.
The TxIRq bit indicates interrupts from different sources. If the transmitter is active and the state changes from sending data to transmitting the end of frame pattern, the transmitter unit sets automatically the interrupt bit. The CRC coprocessor sets TxIRq after having processed all data from the FIFO buffer. This is indicated by the flag CRCReady = 1. If the E2Prom programming has finished the TxIRq bit is set, indicated by the bit E2Ready = 1.
The RxIRq flag indicates an interrupt when the end of the received data is detected.
The flag IdleIRq is set if a command finishes and the content of the command register changes to idle.
The flag HiAlertIRq is set to 1 if the HiAlert bit is set to one, that means the FIFO buffer has reached the level
indicated by the bit WaterLevel, see chapter 7.4.
The flag LoAlertIRq is set to 1 if the LoAlert bit is set to one, that means the FIFO buffer has reached the
level indicated by the bit WaterLevel, see chapter 7.4.

Interrupt Flag Interrupt Source Is set automatically, when
TimerIRq Timer Unit the timer counts from 1 to 0
  Transmitter a data stream, transmitted to the card, ends
TxIRq CRC-Coprocessor all data from the FIFO buffer has been processed
  E²PROM all data from the FIFO buffer has been programmed
RxIRq Receiver a data stream, received from the card, ends
IdleIRq Command Register a command execution finishes
HiAlertIRq FIFO-buffer the FIFO-buffer is getting full
LoAlertIRq FIFO-buffer the FIFO-buffer is getting empty

Table 8-1: Interrupt Sources

Implementation of Interrupt Request Handling
The MF RC500 informs the μ-Processor about the interrupt request source by setting the according bit in the
InterruptRq Register. The relevance of each interrupt request bit as source for an interrupt may be masked
with the interrupt enable bits of the InterruptEn Register.

Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
InterruptEn SetIEn rfu TimerIEn TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn
InterruptRq SetIRq rfu TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq

Table 8-2: Interrupt Control Registers
If any interrupt request flag is set to 1 (showing that an interrupt request is pending) and the corresponding interrupt enable flag is set the status flag IRq in the PrimaryStatus Register is set to 1. Furthermore different interrupt sources can be set active simultaneously. Therefore, all interrupt request bits are ‘OR’ed and connected to the flag IRq and forwarded to pin IRQ.

The interrupt request bits are set automatically by the internal state machines of the MF RC500. Additionally the μ-Processor has access in order to set or to clear them. A special implementation of the InterruptRq and the InterruptEn Register allows to change the status of a single bit without influencing the other ones. If a specific interrupt register shall be set to one, the bit SetIxx has to be set to 1 and simultaneously the specific bit has to be set to 1 too. Vice versa, if a specific interrupt flag shall be cleared, a zero has to be written to the SetIxx and simultaneously the specific address of the interrupt register has to be set to 1. If a bit content shall not be changed during the setting or clearing phase a zero has to be written to the specific bit location.
Example: writing 3Fhex to the InterruptRq Register clears all bits as SetIRq in this case is set to 0 and all other bits are set to 1. Writing 81hex sets bit LoAlertIRq to 1 and leaves all other bits untouched.

Configuration of Pin IRQ
The logic level of the status flag IRq is visible at pin IRQ. In addition, the signal on pin IRQ may be controlled by the following bits of the IRQPinConfig Register:
–IRQInv: if set to 0, the signal on pin IRQ is equal to the logic level of bit IRq.
If set to 1, the signal on pin IRQ is inverted with respect to bit IRq.
–IRQPushPull: if set to 1, pin IRQ has standard CMOS output characteristics, otherwise it is an open drain
output and an external resistor is necessary to achieve a HIGH level at this pin.
Note: During the Reset Phase (see 11.2) IRQInv is set to 1 and IRQPushPull to 0. This results in a high impedance at pin IRQ.

Register Overview Interrupt Request System
The following table shows the related flags of the Interrupt Request System in alphabetic order.

Flags Register Address Register, bit position
HiAlertIEn InterruptEn 0×06, bit 1
HiAlertIRq InterruptRq 0×07, bit 1
IdleIEn InterruptEn 0×06, bit 2
IdleIRq InterruptRq 0×07, bit 2
IRq PrimaryStatus  0×03, bit 3
IRQInv IRQPinConfig 0×07, bit 1
IRQPushPull IRQPinConfig 0×07, bit 0
LoAlertIEn InterruptEn 0×06, bit 0
LoAlertIRq InterruptRq 0×07, bit 0
RxIEn InterruptEn 0×06, bit 3
RxIRq InterruptRq 0×07, bit 3
SetIEn InterruptEn 0×06, bit 7
SetIRq InterruptRq  0×07, bit 7
TimerIEn InterruptEn 0×06, bit 5
TimerIRq InterruptRq 0×07, bit 5
TxIEn InterruptEn 0×06, bit 4
TxIRq InterruptRq 0×07, bit 4

Table 8-3 Registers associated with the Interrupt Request System