Highly Integrated ISO14443A Reader IC, MF RC500

REGISTER BIT BEHAVIOUR
Bits and flags for different registers behave differently, depending on their functions. In principle bits with same behaviour are grouped in common registers.

Abbreviation Behaviour Description
r/w read and
write
These bits can be written and read by the μ-Processor. Since they are used only for control means, there content is not influenced by internal state machines, e.g. the TimerReload-Register may be written and read by the μ-Processor. It will also be read by internal state machines, but never changed by them.
dy dynamic These bits can be written and read by the μ-Processor. Nevertheless, they may also be written automatically by internal state machines, e.g. the Command-Register changes its value automatically after the execution of the actual command.
r read only These registers hold flags, which value is determined by internal states only,e.g. the ErrorFlag-Register can not be written from external but shows internal states.
w write only These registers are used for control means only. They may be written by the μ-Processor but can not be read. Reading these registers returns an undefined value, e.g. the TestAnaSelect-Register is used to determine the signal on pin AUX, but it is not possible to read its content.

Table 5-2: Behaviour of Register Bits and its Designation

Description of the bits  
Bit Symbol Function
7 UsePageSelect If set to 1, the value of PageSelect is used as register address A5, A4, and A3.The LSBbits of the register address are defined by the address pins or the internal address latch, respectively.If set to 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Table 4-2.
6-3 0000 Reserved for future use.
2-0 PageSelect The value of PageSelect is used only if UsePageSelect is set to 1. In this case, it
specifies the register page (which is A5, A4, and A3 of the register address).

Command Register
Starts and stops the command execution.

Description of the bits  
Bit Symbol Function
7 IFDetectBusy Shows the status of Interface Detection Logic:
Set to 0 means ‘Interface Detection finished successfully’,
Set to 1 signs ‘Interface Detection Ongoing’.
6 0 Reserved for future use.
5-0 Command Activates a command according the Command Code.
Reading this register shows, which command is actually executed.

FIFOData Register
In- and output of the 64 byte FIFO buffer.

Description of the bits  
Bit Symbol Function
7-0 FIFOData Data input and output port for the internal 64 byte FIFO buffer. The FIFO buffer
acts as parallel in/parallel out converter for all data stream in- and outputs.

 PrimaryStatus Register
Status flags of the receiver, transmitter and the FIFO buffer.

Description of the bits    
Bit Symbol Function
7 0 Reserved for future use.
6-4 ModemState ModemState shows the state of the transmitter and receiver state machines.
State Name of State Description
000 Idle Neither the transmitter nor the receiver is in operation,
since none of them is started or
since none of them has input data.
001 TxSOF Transmitting the ‘Start Of Frame’ Pattern.
010 TxData Transmitting data from the FIFO buffer (or redundancy
check bits).
011 TxEOF Transmitting the ‘End Of Frame’ Pattern.
100 GoToRx1 Intermediate state, when receiver starts.
GoToRx2 Intermediate state, when receiver finishes.
101 PrepareRx Waiting until the time period selected in the RxWait
Register is expired.
110 AwaitingRx Receiver activated; Awaiting an input signal at pin Rx.
111 Receiving Receiving data.
3 IRQ This bit shows, if any interrupt source requests attention (with respect to the
setting of the interrupt enable flags in the InterruptEn Register).
2 Err This bit is set to 1, if any error flag in the ErrorFlag Register is set.
1 HiAlert Is set to 1, when the number of bytes stored in the FIFO buffer fulfil the following
equation: HiAlert = (64 − FIFOLength) ≤ WaterLevel
Example: FIFOLength=60, WaterLevel=4 ⇒ HiAlert =1
FIFOLength=59, WaterLevel=4 ⇒ HiAlert =0
0 LoAlert Is set to 1, when the number of bytes stored in the FIFO buffer fulfil the following
equation: LoAlert = FIFOLength ≤ WaterLevel
Example: FIFOLength=4, WaterLevel=4 ⇒ LoAlert =1
FIFOLength=5, WaterLevel=4 ⇒ LoAlert =0

 

FIFOLength Register
Number of bytes buffered in the FIFO.

Description of the bits  
Bit Symbol Function
7 0 Reserved for future use.
6-0 FIFOLength Indicates the number of bytes stored in the FIFO buffer. Writing to the FIFOData
Register increments, reading decrements FIFOLength.

SecondaryStatus Register
Diverse Status flags.

Description of the bits  
Bit Symbol Function
7 Trunning If set to 1, the MF RC 500’s timer unit is running, e.g. the counter will decrement
the Timer Value Register with the next timer clock.
6 E2Ready If set to 1, the MF RC 500 has finished programming the E2PROM.
5 CRCReady If set to 1, the MF RC 500 has finished calculating the CRC.
4-3 00 Reserved for future use.
2-0 RxLastBits Show the number of valid bits in the last received byte. If zero, the whole byte is
valid.

InterruptEn Register
Control bits to enable and disable passing of interrupt requests.

Description of the bits  
Bit Symbol Function
7 SetIEn SetIEn Set to 1 SetIEn defines that the marked bits in the InterruptEn Register are set,
Set to 0 clears the marked bits.
6 0 Reserved for future use.
5 TimerIEn Allows the timer interrupt request (indicated by bit TimerIRq) to be propagated to
pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn.
4 TxIEn Allows the transmitter interrupt request (indicated by bit TxIRq) to be propagated
to pin IRQ. This bit can not be set or cleared directly but only by means of bit
SetIEn.
3 RxIEn Allows the receiver interrupt request (indicated by bit RxIRq) to be propagated to
pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn.
2 IdleIEn Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to pin
IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn.
1 HiAlertIEn Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be
propagated to pin IRQ. This bit can not be set or cleared directly but only by
means of bit SetIEn.
0 LoAlertIEn Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be
propagated to pin IRQ. This bit can not be set or cleared directly but only by
means of bit SetIEn.

InterruptRq Register
Interrupt request flags.

Description of the bits  
Bit Symbol Function
7 SetIEn Set to 1, SetIRq defines that the marked bits in the InterruptRq Register are set.
Set to 0 defines, that the marked bits in the InterruptRq Register are cleared.
6 0 Reserved for future use.
5 TimerIEn Set to 1, when the timer decrements the TimerValue Register to zero.
4 TxIEn Set to 1, when one of the following events occurs:
Transceive Command: All data transmitted.
Auth1 and Auth2 Command: All data transmitted.
WriteE2 Command: All data is programmed.
CalcCRC Command: All data is processed.
3 RxIEn This bit is set to 1, when the receiver terminates.
2 IdleIEn This bit is set to 1, when a command terminates by itself e.g. when the Command
Register changes its value from any command to the Idle Command.
If an unknown command is started bit IdleIRq is set.
Starting the Idle Command by the μ-Processor does not set bit IdleIRq.
1 HiAlertIEn This bit is set to 1, when bit HiAlert is set. In opposite to HiAlert, HiAlertIRq stores
this event and can only be reset by means of bit SetIRq.
0 LoAlertIEn This bit is set to 1, when bit LoAlert is set. In opposite to LoAlert, LoAlertIRq
stores this event and can only be reset by means of bit SetIRq.

 

Control Register
Diverse control flags, e.g.: timer, power saving.

Description of the bits  
Bit Symbol Function
7-6 00 Reserved for future use
5 StandBy Setting this bit to 1 enters the Soft PowerDown Mode. This means, internal
current consuming blocks switch off, the oscillator keeps running.
4 PowerDown Setting this bit to 1 enters the Soft PowerDown Mode. This means, internal
current consuming blocks switch off including the oscillator.
3 Crypto1On This bit indicates, that the Crypto1 unit is switched on and therefore all data
communication with the card is encrypted.
This bit can only be set to 1 by a successful execution of the Authent2 Command.
2 TStopNow Setting this bit to 1 stops the timer immediately.
Reading this bit will always return 0.
1 TStartNow Setting this bit to 1 starts the timer immediately.
Reading this bit will always return 0.
0 FlushFIFO Setting this bit to 1clears the internal FIFO-buffer’s read- and write-pointer
(FIFOLength becomes 0) and the flag FIFOOvfl immediately.
Reading this bit will always return 0.

ErrorFlag Register
Error flags showing the error status of the last executed command.

Description of the bits  
Bit Symbol Function
7 0 Reserved for future use.
6 KeyErr This bit is set to 1, if the LoadKeyE2 or the LoadKey Command recognises, that
the input data is not coded according to the Key format definition.
This bit is set to 0 starting the LoadkeyE2 or the LoadKey command.
5 AccessErr This bit is set to 1, if the access rights to the E²PROM are violated.
This bit is set to 0 starting an E²PROM related command.
4 FIFOOvfl This bit is set to 1, if the μ-Processor or a MF RC500’s internal state machine
(e.g. receiver) tries to write data into the FIFO buffer although the FIFO buffer is
already full.
3 CRCErr This bit is set to 1, if RxCRCEn is set and the CRC fails. It is cleared to 0
automatically at receiver start phase during the state PrepareRx.
2 FramingErr This bit is set to 1, if the SOF is incorrect. It is cleared automatically at receiver
start (that is during the state PrepareRx).
1 ParityErr This bit is set to 1, if the parity check has failed. It is cleared automatically at
receiver start (that is during the state PrepareRx).
0 CollErr This bit is set to 1, if a bit-collision is detected. It is cleared automatically at
receiver start (that is during the state PrepareRx).

CollPos Register
Bit position of the first bit collision detected on the RF- interface.

Description of the bits  
Bit Symbol Function
7-0 CollPos This register shows the bit position of the first detected collision in a received
frame.
Example:
0×00 indicates a bit collision in the start bit
0×01 indicates a bit collision in the 1st bit
0×08 indicates a bit collision in the 8th bit

TimerValue Register
actual value of the timer.

Description of the bits  
Bit Symbol Function
7-0 TimerValue This register shows the actual value of the timer counter.

CRCResultLSB Register
LSB of the CRC-Coprocessor register.

Description of the bits  
Bit Symbol Function
7-0 CRCResultLSB This register shows the actual value of the least significant byte of the CRC
register. It is valid only if bit CRCReady is set to 1.

 

CRCResultMSB Register
MSB of the CRC-Coprocessor register.

Description of the bits  
Bit Symbol Function
7-0 CRCResultLSB This register shows the actual value of the most significant byte of the CRC
register. It is valid only if bit CRCReady is set to 1.
For 8-bit CRC calculation the registers value is undefined.

BitFraming Register
Adjustments for bit oriented frames.

Description of the bits  
Bit Symbol Function
7 0 Reserved for future use
6-4 RxAlign Used for reception of bit oriented frames: RxAlign defines the bit position for the
first bit received to be stored in the FIFO. Further received bits are stored in the
following bit positions.
After reception, RxAlign is cleared automatically.
Example: RxAlign = 0: the LSB of the received bit is stored at bit 0,
second received bit is stored at bit position 1
RxAlign = 1: the LSB of the received bit is stored at bit 1,
second received bit is stored at bit position 2
RxAlign = 7: the LSB of the received bit is stored at bit 7,
second received bit is stored in the following byte
at bit position 0
3 0 reserved for future use
2-0 TxLastBits Used for transmission of bit oriented frames: TxLastBits defines the number of
bits of the last byte that shall be transmitted. A 000 indicates that all bits of the last
byte shall be transmitted.
After transmission, TxLastBits is cleared automatically.

TxControl Register
Controls the logical behaviour of the antenna pin TX1 and TX2.

Description of the bits  
Bit Symbol Function
7 0 This value shall not be changed
6-5 Modulator
Source
Selects the source for the modulator input:
00: LOW
01: HIGH
10: Internal Coder
11: Pin MFIN
4 1 This value shall not be changed
3 TX2Inv Set to 1, the output signal on pin TX2 will deliver an inverted 13.56 MHz energy
carrier.
2 TX2Cw Set to 1, the output signal on pin TX2 will deliver continuously the un-modulated
13.56 MHz energy carrier.
Setting TX2Cw to 0 enables modulation of the 13.56 MHz energy carrier.
1 TX2RFEn Set to 1, the output signal on pin TX2 will deliver the 13.56 MHz energy carrier
modulated by the transmission data.
If TX2RFEn is 0, TX2 drives a constant output level.
0 TX1RFEn Set to 1, the output signal on pin TX1 will deliver the 13.56 MHz energy carrier
modulated by the transmission data.
If TX1RFEn is 0, TX1 drives a constant output level.

CwConductance Register
Selects the conductance of the antenna driver pins TX1 and TX2.

Description of the bits  
Bit Symbol Function
7-6 00 These values shall not be changed
5-0 GsCfgCW The value of this register defines the conductance of the output driver. This may
be used to regulate the output power and subsequently current consumption and
operating distance.

PreSet13 Register

ModWidth Register

Description of the bits  
Bit Symbol Function
7-0 ModWidth This register defines the width of the modulation pulse according to
Tmod = 2⋅(ModWidth +1) / fc .

PreSet16 Register

RxControl1 Register
controls receiver behaviour.

Description of the bits  
Bit Symbol Function
7-2 011100 011100 These values shall not be changed
1-0 Gain This register defines the receivers signal voltage gain factor:
00: 20 dB
01: 24 dB
10: 31 dB
11: 35 dB

DecoderControl Register
controls decoder behaviour.

Description of the bits  
Bit Symbol Function
7 0 This value shall not be changed
6 RxMultiple If set to 0, after receiving of the Frame the receiver is deactivated.
If set to 1, it is possible to receive more than one Frame.
5 ZeroAfterColl If set to 1, any bits received after a bit-collision are masked to zero. This eases
resolving the anti-collision procedure defined in ISO14443-A.
4-0 01000 These values shall not be changed

BitPhase Register
selects the bit-phase between transmitter and receiver clock.

Description of the bits  
Bit Symbol Function
7-0 BitPase Defines the phase relation between transmitter and receiver clock.
Note: The correct value of this register is essential for proper operation.

RxThreshold Register
selects thresholds for the bit decoder.

Description of the bits  
Bit Symbol Function
7-4 MinLevel Defines the minimum signal strength at the decoder input that shall be accepted.
If the signal strength is below this level, it is not evaluated.
3-0 CollLevel CollLevel Defines the minimum signal strength at the decoder input that has to be reached
by the weaker half-bit of the Manchester-coded signal to generate a bit-collision
relatively to the amplitude of the stronger half-bit.

PreSet1D Register

RxControl2 Register
controls decoder behaviour and defines the input source for the receiver.

Description of the bits  
Bit Symbol Function
7 RcvClkSelI If set to 1, the I-clock is used for the receiver clock.
0 indicates, the Q-clock is used. I-clock and Q-clock are 90° phase shifted to each
other
6 RxAutoPD If set to 1, the receiver circuit is automatically switched on before receiving and
switched off afterwards. This may be used to reduce current consumption.
If set to 0, the receiver is always activated.
5-2 0000 These values shall not be changed
1-0 DecoderSource Selects the source for the decoder input:
00: Low
01: Internal Demodulator
10: A subcarrier modulated Manchester coded signal at Pin MFIN
11: A baseband Manchester coded signal at Pin MFIN

ClockQControl Register
controls clock generation for the 90° phase shifted Q-channel clock.

Description of the bits  
Bit Symbol Function
7 ClkQ180Deg If the Q-clock is phase shifted more than 180° compared to the I-clock, this bit is
set to 1, otherwise it is 0.
6 ClkQCalib If this bit is 0, the Q-clock is calibrated automatically after the Reset Phase and
after data reception from the card.
If this bit is set to 1, no calibration is performed automatically.
5 0 This value shall not be changed
4-0 ClkQDelay This register shows the number of delay elements actually used to generate a 90°
phase shift of the I-clock to obtain the Q-clock.
It can be written directly by the μ-Processor or by the automatic calibration cycle.

RxWait Register
Selects the time interval after transmission, before receiver starts.

Description of the bits  
Bit Symbol Function
7-0 RxWait After data transmission, the activation of the receiver is delayed for RxWait bitclocks.
During this ‘frame guard time’ any signal at pin Rx is ignored.

ChannelRedundancy Register
Selects kind and mode of checking the data integrity on the RF-channel.

Description of the bits  
Bit Symbol Function
7-6 00 This value shall not be changed
5 CRC3309 If set to 1, CRC-calculation is done according ISO/IEC3309.
Note: For usage according to ISO14443-A this bit has to be 0.
4 CRC8 If set to 1, an 8-bit CRC is calculated.
If set to 0, a 16-bit CRC is calculated.
3 RxCRCEn If set to 1, the last byte(s) of a received frame is/are interpreted as CRC byte/s.
If the CRC itself is correct the CRC byte(s) is/are not passed to the FIFO.
In case of an error, the CRCErr flag is set.
If set to 0, no CRC is expected.
2 TxCRCEn If set to 1, a CRC is calculated over the transmitted data and the CRC byte(s) are
appended to the data stream.
If set to 0, no CRC is transmitted.
1 ParityOdd If set to 1, an odd parity is generated or expected, respectively.
If set to 0 an even parity is generated or expected, respectively.
Note: For usage according to ISO14443-A this bit has to be 1.
0 ParityEn If set to 1, a parity bit is inserted in the transmitted data stream after each byte
and expected in the received data stream after each byte.
If set to 0, no parity bit is inserted or expected.

CRCPresetLSB Register
LSB of the preset value for the CRC register.

Description of the bits  
Bit Symbol Function
7-0 CRCPresetLSB CRCPresetLSB defines the starting value for CRC-calculation. This value is
loaded into the CRC at the beginning of transmission, reception and the CalcCRC
Command, if the CRC calculation is enabled.

CRCPresetMSB Register
MSB of the preset value for the CRC register.

Description of the bits  
Bit Symbol Function
7-0 CRCPresetMSB CRCPresetMSB defines the starting value for CRC-calculation. This value is
loaded into the CRC at the beginning of transmission, reception and the CalcCRC
Command, if the CRC calculation is enabled.
Note: This register is not relevant, if CRC8 is 1.

 

Description of the bits  
Bit Symbol Function
7 7-3 These values shall not be changed
2-0 MFOUTSelect MFOUTSelect defines which signal is routed to pin MFOUT.
000 Constant Low
001 Constant High
010 Modulation Signal (envelope) from internal coder, Miller coded
011 Serial data stream, not Miller coded
100 Output signal of the energy carrier demodulator (card modulation
signal)
101 Output signal of the subcarrier demodulator (Manchester coded card
signal)
110 RFU
111 RFU

PreSet27 Register

FIFOLevel Register
Defines the level for FIFO under- and overflow warning.

Description of the bits  
Bit Symbol Function
7-6 00 These values shall not be changed
5-0 WaterLevel This register defines, the warning level of the MF RC500 for the μ-Processor for a
FIFO-buffer over- or underflow:
HiAlert is set to 1, if the remaining FIFO-buffer space is equal or less than
WaterLevel bytes in the FIFO-buffer.
LoAlert is set to 1, if equal or less than WaterLevel bytes are in the FIFO-buffer,.

TimerClock Register
Selects the divider for the timer clock.

Description of the bits  
Bit Symbol Function
7-6 00 These values shall not be changed
5 TAutoRestart If set to 1, the timer automatically restart its count-down from TReloadValue,
instead of counting down to zero.
If set to 0 the timer decrements to zero and the bit TimerIRq is set to 1.
4-0 TPreScaler Defines the timer clock fTimer. TPreScaler can be adjusted from 0 up to 21. The
following formula is used to calculate fTimer :
fTimer = 13.56 MHz / 2TPreScaler.

TimerControl Register
Selects start and stop conditions for the timer.

Description of the bits  
Bit Symbol Function
7-4 0000 These values shall not be changed
3 TStopRxEnd If set to 1, the timer stops automatically when data reception ends.
0 indicates, that the timer is not influenced by this condition.
2 TStopRxBegin If set to 1, the timer stops automatically, when the first valid bit is received.
0 indicates, that the timer is not influenced by this condition.
1 TStartTxEnd If set to 1, the timer starts automatically when data transmission ends. If the timer
is already running, the timer restarts by loading TReloadValue into the timer.
0 indicates, that the timer is not influenced by this condition.
0 TStartTxBegin If set to 1, the timer is starts automatically when the first bit is transmitted. If the
timer is already running, the timer restarts by loading TReloadValue into the timer.
0 indicates, that the timer is not influenced by this condition.

TimerReload Register
Defines the preset value for the timer.

Description of the bits  
Bit Symbol Function
7-0 TReloadValue With a start event the timer loads with the TreloadValue. Changing this register
affects the timer only with the next start event.
If TReloadValue is set to 0, the timer cannot start.

IRQPinConfig Register
Configures the output stage for pin IRQ.

Description of the bits  
Bit Symbol Function
7-2 000000 These values shall not be changed
1 IRQInv If set to 1, the signal on pin IRQ is inverted with respect to bit IRq.
0 indicates, that the signal on pin IRQ is equal to bit IRQ.
0 IRQPushPull If set to 1, pin IRQ works as standard CMOS output pad.
0 indicates, that pin IRQ works as open drain output pad.

 

Flag(s) Register Address Register, Bit Position
AccessErr ErrorFlag 0x0A, bit 5
BitPhase BitPhase 0x1B, bits 7:0
ClkQ180Deg ClockQControl 0x1F, bit 7
ClkQCalib ClockQControl 0x1F, bit 6
ClkQDelay ClockQControl 0x1F, bits 4:0
CollErr ErrorFlag 0x0A, bit 0
CollLevel RxThreshold 0x1C, bits 3:0
CollPos CollPos 0x0B, bits 7:0
Command Command 0×01, bits 5:0
CRC3309 ChannelRedundancy 0×22, bit 5
CRC8 ChannelRedundancy 0×22, bit 4
CRCErr ErrorFlag 0x0A, bit 3
CRCPresetLSB CRCPresetLSB 0×23, bits 7:0
CRCPresetMSB CRCPresetMSB 0×24, bits 7:0
CRCReady SecondaryStatus 0×05 , bit 5
CRCResultMSB CRCResultMSB 0x0E, bits 7:0
CRCResultLSB CRCResultLSB 0x0D, , bits 7:0
Crypto1On Control 0×09, bit 3
DecoderSource RxControl2 0x1E, bits 1:0
E2Ready SecondaryStatus 0×05, bit 6
Err PrimaryStatus 0×03, bit 2
FIFOData FIFOData 0×02, bits 7:0
FIFOLength FIFOLength 0×04, bits 7:0
FIFOOvfl ErrorFlag 0x0A, bit 4
FlushFIFO Control 0×09, bit 0
FramingErr ErrorFlag 0x0A, bit 2
Gain RxControl1 0×19, bits 1:0
GsCfgCW CWConductance 0×12, bits 5:0
HiAlert PrimaryStatus 0×03, bit 1
HiAlertIEn InterruptEn 0×06, bit 1
HiAlertIRq InterruptRq 0×07, bit 1
IdleIEn InterruptEn 0×06, bit 2

 

Flag(s) Register Address Register, Bit Position
IdleIRq InterruptRq 0×07, bit 2
IFDetectBusy Command 0×01, bit 7
IRq PrimaryStatus 0×03, bit 3
IRQInv IRQPinConfig 0x2D, bit 1
IRQPushPull IRQPinConfig 0x2D, bit 0
KeyErr ErrorFlag 0x0A, bit 6
LoAlert PrimaryStatus 0×03, bit 0
LoAlertIEn InterruptEn 0×06, bit 0
LoAlertIRq InterruptRq 0×07, bit 0
MFOUTSelect MFOUTSelect 0×26, bits 2:0
MinLevel RxThreshold 0x1C, bits 7:4
ModemState PrimaryStatus 0×03 , bit 6:4
ModulatorSource TxControl 0×11, bits 6:5
ModWidth ModWidth 0×15, bits /:0
PageSelect Page 0×00, 0×08, 0×10, 0×18, 0×20, 0×28, 0×30, 0×38, bits 2:0
ParityEn ChannelRedundancy 0×22, bit 0
ParityErr ErrorFlag 0x0A, bit 1
ParityOdd ChannelRedundancy 0×22 , bit 1
PowerDown Control 0×09, bit4
RcvClkSelI RxControl2 0x1E, bit 7
RxAlign BitFraming 0x0F, bits 6:4
RxAutoPD RxControl2 0x1E, bit 6
RxCRCEn ChannelRedundancy 0×22, bit 3
RxIEn InterruptEn 0×06, bit 3
RxIRq InterruptRq 0×07, bit 3
RxLastBits SecondaryStatus 0×05, bits 2:0
RxMultiple DecoderControl 0x1A, bit 6
RxWait RxWait 0×21, bits 7:0
SetIEn InterruptEn 0×06, bit 67
SetIRq InterruptRq 0×07, bit 7
SignalToMFOUT TestDigiSelect 0x3D, bit 7
StandBy Control 0×09, bit 5
TAutoRestart TimerClock 0x2A, bit 5

 

Flag(s) Register Address Register, Bit Position
TestAnaOutSel TestAnaSelect 0x3A, bits 6:4
TestDigiSignalSel TestDigiSelect 0x3D, bit 6:0
TimerIEn InterruptEn 0×06, bit 5
TimerIRq InterruptRq 0×07, bit 5
TimerValue TimerValue 0x0C, bits 7:0
TPreScaler TimerClock 0x2A, bits 4:0
TReloadValue TimerReload 0x2C, bits 7:0
TRunning SecondaryStatus 0×05, bit 7
TStartTxBegin TimerControl 0x2B, bit 0
TStartTxEnd TimerControl 0x2B, bit 1
TStartNow Control 0×09, bit 1
TStopRxBegin TimerControl 0x2B, bit 2
TStopRxEnd TimerControl 0x2B, bit 3
TStopNow Control 0×09, bit 2
TX1RFEn TxControl 0×11, bit 0
TX2Cw TxControl 0×11, bit 3
TX2Inv TxControl 0×11, bit 3
TX2RFEn TxControl 0×11, bit 1
TxCRCEn ChannelRedundancy 0×22, bit 2
TxIEn InterruptEn 0×06, bit 4
TxIRq InterruptRq 0×07, bit 4
TxLastBits BitFraming 0x0F, bits 2:0
UsePageSelect Page 0×00, 0×08, 0×10, 0×18, 0×20, 0×28, 0×30, 0×38, bit 7
WaterLevel FIFOLevel 0×29, bits 5:0
ZeroAfterColl DecoderControl 0x1A, bit 5

 

Modes of Register Addressing
There are three mechanisms to operate the MF RC500:
–Initiating functions and controlling data manipulation by executing commands
–Configuring electrical and functional behaviour via a set of configuration bits
–Monitoring the state of the MF RC500 by reading status flags
The commands, configurations bits and flags are accessed via the µ-Processor interface. The MF RC500 can internally address 64 registers. This basically requires six address lines.

PAGING MECHANISM
The MF RC500 register set is segmented into 8 pages with 8 register each. The Page-Register can always be addressed, no matter which page is currently selected.

DEDICATED ADDRESS BUS
Using the MF RC500 with dedicated address bus, the µ-Processor defines three address lines via the address pins A0, A1, and A2. This allows addressing within a page. To switch between registers in different pages the paging mechanism needs then to be used.
The following table shows how the register address is assembled:

Register Bit: UsePageSelect   Register-Address      
1 PageSelect2  PageSelect1 PageSelect0 A2 A1 A0

 

MULTIPLEXED ADDRESS BUS
Using the MF RC500 with multiplexed address bus, the µ-Processor may define all six address lines at once.
In this case either the paging mechanism or linear addressing may be used.
The following table shows how the register address is assembled:

Interface Bus Type Register Bit: UsePageSelect   Register-Address      
Multiplexed Address Bus (paging mode) 1 PageSelect2  PageSelect1 PageSelect0 AD2 AD1 AD0
Multiplexed Address Bus (linear addressing) 0 AD5 AD4 AD3 AD2 AD1 AD0

 

Table 5-4: Multiplexed Address Bus: Assembling the Register Address