Highly Integrated ISO14443A Reader IC, MF RC500

PARALLEL INTERFACE
Overview of Supported μ-Processor Interfaces

The MF RC500 supports direct interfacing of various μ-Processor. Alternatively the Enhanced Parallel Port (EPP) of personal computers can be connected directly. The following table shows the parallel interface signals supported by the MF RC500:

Bus Control Signals Bus Separated Address and Data Bus Multiplexed Address and Data Bus
Separated Read and Write Strobes control NRD, NWR, NCS NRD, NWR, NCS, ALE
address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5
data D0 … D7 AD0 … AD7
Common Read and Write Strobes control R/NW, NDS, NCS R/NW, NDS, NCS, AS
address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5
data D0 … D7 AD0 … AD7
Common Read and Write
Strobe with Handshake
(EPP)
control   nWrite, nDStrb, nAStrb, nWait
address   AD0, AD1, AD2, AD3, AD4, AD5
data   AD0 … AD7
Table 4-1: Supported μ-Processor Interface Signals

 

Automatic μ-Processor Interface Type Detection
After every Power-On or Hard Reset, the MF RC500 also resets its parallel μ-Processor interface mode and checks the current μ-Processor interface type. The MF RC500 identifies the μ-Processor interface by means of the logic levels on the control pins after the Reset Phase. This is done by a combination of fixed pin connections (see below) and a dedicated initialisation routine (see 11.4). Connection to Different μ-Processor Types The connection to different μ-Processor types is shown in the following table:

MF RC500 Parallel Interface Type
Separated Read/Write Strobe Common Read/Write Strobe
Dedicated
Address Bus
Multiplexed
Address Bus
Dedicated
Address Bus
Multiplexed
Address Bus
Multiplexed
Address Bus with
Handshake
ALE HIGH ALE HIGH AS nAStrb
A2 A2 LOW A2 LOW HIGH
A1 A1 HIGH A1 HIGH HIGH
A0 A0 HIGH A0 LOW nWait
NRD NRD NRD NRD NRD nDStrb
NWR NWR NWR R/NW R/NW nWait
NCS NCS NCS NCS NCS LOW
D7 … D0 D7 … D0 AD7 … AD0 D7 … D0 AD7 … AD0 AD7 … AD0
Table 4-2: Connection Scheme for Detecting the Parallel Interface Type

 

MF RC500 REGISTER SET    
MF RC500 Registers Overview    
Page Page Address Register Name Function
Page 0: Command and Status 0 Page selects the register page
1 Command starts (and stops) the command execution
2 FIFOData in- and output of 64 byte FIFO buffer
3 PrimaryStatus status flags of the receiver and transmitter and of the FIFO buffer
4 FIFOLength number of bytes buffered in the FIFO
5 SecondaryStatus diverse status flags
6 InterruptEn control bits to enable and disable passing of interrupt requests
7 InterruptRq interrupt request flags
 
Page 1: Control and Status 8 Page selects the register page
9 Control diverse control flags e.g.: timer, power saving
A ErrorFlag error flags showing the error status of the last command executed
B CollPos bit position of the first bit collision detected on the RF-interface
C TimerValue actual value of the timer
D CRCResultLSB LSB of the CRC-Coprocessor register
E CRCResultMSB MSB of the CRC-Coprocessor register
F BitFraming adjustments for bit oriented frames
 
Page 2: Transmitter and Coder Control 10 Page selects the register page
11 TxControl controls the logical behaviour of the antenna driver pins TX1 and TX2
12 CWConductance selects the conductance of the antenna driver pins TX1 and TX2
13 PreSet13 these values shall not be changed
14 PreSet14 these values shall not be changed
15 ModWidth selects the width of the modulation pulse
16 PreSet16 these values shall not be changed
17 PreSet17 these values shall not be changed
 
Page 3: Receiver and Decoder Control 18 Page selects the register page
19 RxControl1 controls receiver behaviour
1A DecoderControl controls decoder behaviour
1B BitPhase selects the bit-phase between transmitter and receiver clock
1C RxThreshold selects thresholds for the bit decoder
1D PreSet1D these values shall not be changed
1E RxControl2 controls decoder behaviour and defines the input source for the receiver
1F ClockQControl controls clock generation for the 90° phase shifted Q-channel clock
 
Page 4: RF-Timing and Channel Redundancy 20 Page selects the register page
21 RxWait selects the time interval after transmission, before receiver starts
22 ChannelRedundancy selects the kind and mode of checking the data integrity on the Rfchannel
23 CRCPresetLSB LSB of the pre-set value for the CRC register
24 CRCPresetMSB MSB of the pre-set value for the CRC register
25 PreSet25 these values shall not be changed
26 MFOUTSelect selects internal signal applied to pin MFOUT
27 PreSet27 these values shall not be changed
 
Page 5: FIFO, Timer and IRQ-Pin Configuration 28 Page selects the register page
29 FIFOLevel defines level for FIFO over– and underflow warning
2A TimerClock selects the divider for the timer clock
2B TimerControl selects start and stop conditions for the timer
2C TimerReload defines the pre-set value for the timer
2D IRQPinConfig configures the output stage of pin IRQ
2E PreSet2E these values shall not be changed
2F PreSet2F these values shall not be changed
 
Page 6: RFU 30 Page selects the register page
31 RFU reserved for future use
32 RFU reserved for future use
33 RFU reserved for future use
34 RFU reserved for future use
35 RFU reserved for future use
36 RFU reserved for future use
37 RFU reserved for future use
 
Page 7: Test Control 38 Page selects the register page
39 RFU reserved for future use
3A TestAnaSelect selects analog test mode
3B RFU reserved for future use
3C RFU reserved for future use
3D TestDigiSelect selects analog test mode
3E RFU reserved for future use
3F RFU reserved for future use
       
Table 5-1: MF RC500 Register Overview