The telephone chip protocol
Data transmission is illustrated here using a phone card containing an Infineon SLE4403 chip as an example. The memory in this IC is bit-oriented, which means that all operations are carried out on individual bits. Other types of chips may have protocols that differ from the protocol described here. However, the basic data transmission principles are the same for all synchronous cards. Data are transmitted using three leads. The bidirectional data lead is used by both the card and the terminal to exchange single-bit data. The clock lead transmits the clock generated by the terminal to the card. This clock provides the reference for the synchronous data transmission. The third connection needed for the data transmission is the control lead. It determines what the chip actually does, based on the states of the other two leads. In principle, complete control of a memory card requires the chip’s logic circuitry to decode four different functions. These are read, write, clear memory and increment the address pointer.
A memory card has a global memory pointer that can be used to address all memory regions bit by bit. If the pointer reaches the upper memory boundary, it rolls over to zero. With a bit-oriented chip design, it then points to the first bit in memory. One of the functions of synchronous data transmission is to reset this pointer to an initial value, which is normally zero. The next function is to read data from the memory. The other two functions are writing and erasing EEPROM bits. Erasing EEPROM bits, which would allow them to be rewritten, is of course blocked in phone cards, since otherwise the cards could be reloaded.

Resetting the address pointer
The address pointer is reset to its initial value of zero by the power-up logic of the card if the clock lead and the control lead are simultaneously at a high level. However, the control pulse must be applied for a somewhat longer interval than the clock pulse, in order to prevent the address from being immediately incremented. The address pointer should be reset to its original value after each activation sequence, since it would otherwise be pointing to an undefined address.

Incrementing the address pointer and reading data
If there is a rising edge on the clock line while the control lead is at a low level, the internal logic of the card increments the address pointer by one. The falling edge of the clock causes the content of the address indicated by the pointer to be placed on the data lead. If the pointer reaches its maximum value, which depends on the size of the memory, it rolls over to zero and thus starts over from the beginning.

Writing to an address
If the address pointer is within a writeable EEPROM region, the value on the data lead can be written to EEPROMby applying a high level to the control lead and then pulling the clock lead low. The length of the write cycle is determined by the duration of the immediately following clock pulse. If the bit was written correctly, the content of the written memory cell appears at the data output.

Erasing bytes
Part of the EEPROMmemory in a typical phone card is always organized as a multi-place octal counter. If a byte has to be erased in this counter due to a carry to the next place, this is performed by the logic circuitry. Erasing a byte in memory is thus somewhat more complicated. The procedure is as follows: if a bit within a byte is written twice in a row, the chip’s hardware logic automatically erases the associated less significant byte. This ensures that a carry to the next higher place occurs, while the lower place is erased without allowing any opportunity for fraud. The four types of access that have been described may vary from chip to chip and also among manufacturers. Another type of data transmission, which by contrast is standardized, is represented by the I2C bus. Many of the newer memory cards use this bus for communicating with the terminal. This naturally has the advantage that different chips, made by different manufacturers, can be used together within a single system. Problems due to several different transmission protocols are thus eliminated, since all chips are mutually compatible at the transmission interface.